Method and apparatus for output deselecting of data during test
US5539753A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 1995 |
| Grant date | Jul 23, 1996 |
| Priority date | — |
| Expiry date | Aug 10, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318516
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A circuit, as a logic circuit or a memory circuit, having testing latches. The testing latches include an input latch, a slave latch, and true and complement output latches. The output of the slave latch is NANDed with a DESELECT signal to deselect the output latches. The testing latches can be used in a method of characterizing or testing a memory or logic integrated circuit with scannable output latches. At least one output latch has an input latch, a slave latch, and an output latch which may contain a Complement Latch, and a True latch. In the testing process an output of the slave latch is NANDed with a deselect signal to allow testing or characterization by masking known "fail" signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.