High-performance, superscalar-based computer system with out-of-order instruction execution
US5539911A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 1992 |
| Grant date | Jul 23, 1996 |
| Priority date | — |
| Expiry date | Jan 8, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches and stores program instruction sets. Each instruction set includes a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instruction sets and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers which are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instructions in-order.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.