Patent · US Expired

Semiconductor arrangement and method for its manufacture

US5541140A · kind A · utility

12Cited by

1References

4Claims

0Family size

Assignee

Robert Bosch GmbH · DE

Inventors

Herbert Goebel · Gräfelfing, DE
Vesna Biallas · Reutlingen, DE
Richard Spitz · Reutlingen, DE
Anton Mindl · Hildesheim, DE

Key dates

Filing date	Jun 23, 1994
Grant date	Jul 30, 1996
Priority date	—
Expiry date	Jun 23, 2014

Classification

Technology area (CPC H)Electricity
CPC primaryH10D8/00
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Semiconductor arrangements, in particular diodes, have a p-layer and two n-layers that are doped to varying degrees of thickness. The p-n junction between the p-layer and the heavily doped n-layer is arranged in the chip so as to allow it to lie completely inside the chip. The p-n junction between the p-layer and the n-layer is situated in the outside areas of the chip. This arrangement does not permit any high field strengths to occur on the outside of the chip and, at the same time, it makes it possible for easily reproducible properties to be achieved. The manufacturing method can also be carried-out outside of a clean room.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.