VDMOS semiconductor device
US5541430A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 30, 1993 |
| Grant date | Jul 30, 1996 |
| Priority date | — |
| Expiry date | Apr 30, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/519
Abstract
In a semiconductor device having a low ON resistance, an n.sup.- -type epitaxial layer (1) is formed on an upper surface of an n.sup.+ -type substrate (8) and p-type diffusion regions (2) are selectively formed on its upper surface, while n-type diffusion regions (3) are further formed on upper surfaces thereof. A gate electrode (5) wrapped up in an oxide film (4) is provided on the upper surface of the n.sup.- -type epitaxial layer (1) and above portions of the p-type diffusion regions (2) held between the n.sup.- -type epitaxial layer (1) and the n.sup.+ -type diffusion regions (3). Grooves (9) are formed in the upper surface of the n.sup.- -type epitaxial layer (1) located under a gate electrode (5) to extend perpendicularly to junction planes between the n.sup.- -type epitaxial layer (1) and the p-type diffusion regions (2). While an ON resistance includes an accumulation resistance (Ra) and a JFET resistance (Rj), these resistances can be reduced since a gate width is increased due to formation of the grooves (9) and a current readily flows downwardly along the grooves (9).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.