Integration of high voltage lateral MOS devices in low voltage CMOS architecture using CMOS-compatible process steps

US5541435A · kind A · utility

Assignee

• HARRIS CORPORATION · US

Inventor

• James D. Beasom · Swindale, US

Key dates

• Filing date: Apr 13, 1994
• Grant date: Jul 30, 1996
• Expiry date: Apr 13, 2014

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/83

Abstract

Region forming steps or interconnect-forming steps through which low voltage CMOS devices are formed in a semiconductor wafer are also employed to simultaneously form one or more regions or layers at selected sites of a substrate where high voltage devices are to be formed. Such selective modification of an already existing mask set designed for low voltage CMOS typography allows additional doping of the substrate or provision of further overlay material to accommodate the effects of high voltage operation of selected areas of the wafer and thereby effectively performs precursor tailoring or modification of those portions of the wafer where a high voltage condition will be encountered.