Testing integrated circuits by consolidating a plurality of digital signals as a multilevel signal
US5541505A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 14, 1993 |
| Grant date | Jul 30, 1996 |
| Priority date | — |
| Expiry date | Sep 14, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2273
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An apparatus for testing a semiconductor integrated circuit includes a plurality of probe lines and a plurality of sense lines which intersect each other to thereby define a plurality of intersections thereby as electrically isolated from each other. An electronic switch device is provided for each intersection for producing a multilevel signal, on an associated sense line, having one of a predetermined number of voltage levels corresponding to various combinations definable by a predetermined number of binary numbers supplied to test points from logic elements to be tested. In a four test point embodiment, four test points are arranged such that each test point is located in a corresponding one of four quadrants defined by a pair of probe and sense lines intersecting each other. Preferably, the integrated circuit is in the form of a gate array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.