Pipelined computer with operand context queue to simplify context-dependent execution flow
US5542058A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 1994 |
| Grant date | Jul 30, 1996 |
| Priority date | — |
| Expiry date | Oct 4, 2014 |
Classification
- Technology area (CPC F)Mechanical Engineering; Lighting; Heating
- CPC primaryF02B2075/025
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A macropipelined microprocessor chip adheres to strict read and write ordering by sequentially buffering operands in queues during instruction decode, then removing the operands in order during instruction execution. Any instruction that requires additional access to memory inserts the requests into the queued sequence (in a specifier queue) such that read and write ordering is preserved. A specifier queue synchronization counter captures synchronization points to coordinate memory request operations among the autonomous instruction decode unit, instruction execution unit, and memory sub-system. The synchronization method does not restrict the benefit of overlapped execution in the pipelined. Another feature is treatment of a variable bit field operand type that does not restrict the location of operand data. Instruction execution flows in a pipelined processor having such an operand type are vastly different depending on whether operand data resides in registers or memory. Thus, an operand context queue (field queue) is used to simplify context-dependent execution flow and increase overlap. The field queue allows the instruction decode unit to issue instructions with variable bit …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.