Method for fabricating crown capacitors for a dram cell
US5543345A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 1995 |
| Grant date | Aug 6, 1996 |
| Priority date | — |
| Expiry date | Dec 27, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
Abstract
A method is provided for fabricating a single crown electrode for a capacitor for semiconductor memory devices. A conductive layer is formed over a multi-layer gate and insulation structure. The conductive layer includes a portion extending through a contact hole to thereby electrically connect the conductive layer with an active region of a transistor formed in the substrate Next, a novel groove is etched in the conductive layer between adjacent memory cells. Sidewall spacers are formed on the groove. The conductive layer is anisotropically etched using the spacers as an etching mask, thereby forming a plurality of electrodes having upright portions. The etching exposes the first insulation layer in the area under the grooves, but leaves a thickness of the base conductive layer to form the bottom of the electrode. The spacers then are removed and a conformal dielectric layer is formed over the surface. Lastly, a top plate electrode is formed over the conformal dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.