Charge stacking on-chip high-voltage generator and method
US5543668A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 16, 1994 |
| Grant date | Aug 6, 1996 |
| Priority date | — |
| Expiry date | Sep 16, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/145
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A charge stacking, high voltage generating circuit is provided wherein a plurality of capacitors are charged in parallel and discharged in series through a single diode to an output terminal. A switching circuit is used to connect each of the capacitors in parallel between a first supply voltage and a second supply voltage during a first half clock cycle. This configuration allows the capacitors to charge during this first half clock cycle. During a second half clock cycle, the switching circuit connects the charged capacitors in series between the first supply voltage and the output terminal through a single diode. The series configuration of the capacitors is such that the voltage at the output terminal is approximately equal to the first supply voltage, plus the sum of the voltages of the charged capacitors, minus the threshold voltage drop across the series diode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.