Semiconductor memory device with redundant decoder available for test sequence on redundant memory cells
US5544106A · kind A · utility
76Cited by
1References
8Claims
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Key dates
| Filing date | Feb 14, 1995 |
| Grant date | Aug 6, 1996 |
| Priority date | — |
| Expiry date | Feb 14, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor dynamic random access memory device is equipped with rows of redundant memory cells for replacing defective rows of regular memory cells therewith, and a redundant system associated with the rows of redundant memory cells is enabled in a test sequence for selectively energizing redundant word lines in response to external address signals so as to eliminate an address pointer only used in the test sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.