Method of maufacturing a semiconductor device having a low resistance gate electrode
US5545578A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 1995 |
| Grant date | Aug 13, 1996 |
| Priority date | — |
| Expiry date | May 15, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a semiconductor device, e.g., an LDD transistor, which includes the steps of forming a gate insulating layer on a semiconductor substrate, forming a polysilicon layer on the gate insulating layer, forming a silicide layer on the polysilicon layer, etching the silicide layer to form a gate-patterned silicide layer, and over-etching the silicide layer to partially etch the polysilicon layer, to thereby form a step in the polysilicon layer, forming an oxidation-prevention spacer on sidewalls of the gate-patterned silicide layer and sidewalls of the polysilicon layer exposed by the step, etching the polysilicon layer, using the oxidation-prevention spacer as an etching mask, to thereby form a gate-patterned polysilicon layer, the gate-patterned silicide layer and the gate-patterned polysilicon layer together comprising a gate electrode, thermally oxidizing exposed portions of the gate insulating layer and exposed portions of the polysilicon layer, to thereby form an oxide layer, and, ion-implanting impurities into the semiconductor substrate, using the resultant structure as an ion-implantation mask, to thereby form source/drain regions in the semiconductor s…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.