Method of making a dram circuit with fin-shaped stacked capacitors
US5545585A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 1996 |
| Grant date | Aug 13, 1996 |
| Priority date | — |
| Expiry date | Jan 29, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/714
Abstract
A novel method is presented for making an array of stacked capacitors on DRAM circuits. Chemical/Mechanical Polishing (CMP) is used to form "globally" a very planar surface on an insulating layer across the substrate. By virtue of this global planarization three additional insulating layers deposited consecutively thereon, also provide a very planar surface for exposing and developing high fidelity (distortion free) photoresist images. Subsequent anisotropic plasma etching of deposited layers on these planar surfaces also provide residue free (strings) structures. Stacked capacitors are then fabricated by etching contact openings in the insulating layers to the source/drain areas of FETs on the substrate. Alternate insulating layers having different etch rates are isotropic wet etched in the contact openings to recess and form fin-shaped profiles in the openings sidewalls. A polysilicon layer is deposited on the planar insulating layer surface and in the contact openings, and patterned forming fin-shaped bottom electrodes. The planar insulating layers are removed, and the capacitors are completed by forming a thin dielectric on the bottom electrode, and depositing and patterning th…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.