Inventor · Baoshan, TW

Chen-Jong Wang

108Patents
21h-index
88Co-inventors
93Inventor score

Filing activity: Apr 27, 1995 → Jan 4, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US9142517B2 Hybrid bonding mechanisms for semiconductor wafers Electricity 210 Active
US9443796B2 Air trench in packages incorporating hybrid bonding Electricity 198 Active
US5668035A Method for fabricating a dual-gate dielectric module for memory with embedded logic technology Electricity 97 Expired
US6037222A Method for fabricating a dual-gate dielectric module for memory embedded logic using salicide technology and polycide technology Electricity 84 Expired
US5607874A Method for fabricating a DRAM cell with a T shaped storage capacitor Electricity 60 Expired
US6017791A Multi-layer silicon nitride deposition method for forming low oxidation temperature thermally oxidized silicon nitride/silicon oxide (no) layer Emerging Cross-Sectional Technologies 57 Expired
US5677557A Method for forming buried plug contacts on semiconductor integrated circuits Electricity 47 Expired
US6015730A Integration of SAC and salicide processes by combining hard mask and poly definition Electricity 39 Expired
US5545584A Unified contact plug process for static random access memory (SRAM) having thin film transistors Electricity 37 Expired
US6620679B1 Method to integrate high performance 1T ram in a CMOS process using asymmetric structure Electricity 33 Expired
US5702989A Method for fabricating a tub structured stacked capacitor for a DRAM cell having a central column Electricity 32 Expired
US5668038A One step smooth cylinder surface formation process in stacked cylindrical DRAM products Electricity 29 Expired
US6004857A Method to increase DRAM capacitor via rough surface storage node plate Electricity 27 Expired
US5591664A Method of increasing the capacitance area in DRAM stacked capacitors using a simplified process Electricity 25 Expired
US5545585A Method of making a dram circuit with fin-shaped stacked capacitors Electricity 25 Expired
US6177340A Method to reduce contact hole aspect ratio for embedded DRAM arrays and logic devices, via the use of a tungsten bit line structure Electricity 24 Expired
US6271125A Method to reduce contact hole aspect ratio for embedded DRAM arrays and logic devices, via the use of a tungsten bit line structure Electricity 24 Expired
US5547892A Process for forming stacked contacts and metal contacts on static random access memory having thin film transistors Emerging Cross-Sectional Technologies 24 Expired
US5607879A Method for forming buried plug contacts on semiconductor integrated circuits Electricity 24 Expired
US5856220A Method for fabricating a double wall tub shaped capacitor Electricity 23 Expired
US5587696A High resistance polysilicon resistor for integrated circuits and method of fabrication thereof Emerging Cross-Sectional Technologies 23 Expired
US6242300A Mixed mode process for embedded dram devices Electricity 20 Expired
US6265301A Method of forming metal interconnect structures and metal via structures using photolithographic and electroplating or electro-less plating procedures Electricity 20 Expired
US5716881A Process to fabricate stacked capacitor DRAM and low power thin film transistor SRAM devices on a single semiconductor chip Emerging Cross-Sectional Technologies 20 Expired
US9960129B2 Hybrid bonding mechanisms for semiconductor wafers Electricity 20 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.