Integrated mosfet device with low resistance peripheral diffusion region contacts and low PN-junction failure memory diffusion contacts
US5545926A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 1994 |
| Grant date | Aug 13, 1996 |
| Priority date | — |
| Expiry date | Oct 7, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
Abstract
A first contact hole for a bit line is formed in an interlayer insulating film, and a polysilicon film is formed on the inner surface of the contact hole and on the interlayer insulating film. Subsequently, the polysilicon film is subjected to isotropic dry etching using a resist as a mask, and the interlayer insulating film is subjected to RIE etching, thereby forming a second contact hole in the interlayer insulating film in a peripheral circuit region. Then, a laminated film is formed on the inner surface of the second contact hole and on the polysilicon film, and the second contact hole is filled with a filling member. The laminated film and the polysilicon film are patterned, thereby forming a bit line in a memory cell region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.