Hierarchical pattern faults for describing logic circuit failure mechanisms
US5546408A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 9, 1994 |
| Grant date | Aug 13, 1996 |
| Priority date | — |
| Expiry date | Jun 9, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318342
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and system (12) for defining and using a pattern fault file (15) having a static pattern fault and/or a dynamic pattern fault. A static pattern fault is represented as a list of required excitation nodes and their values, as well as a fault propagation point. The fault propagation point is defined to be a net or node in a circuit to be tested where the defect's effect first appears once it has been excited. A dynamic pattern fault adds to this structure an initial value list of nodes and their required initial values. The dynamic-pattern fault is employed to advantage when a two pattern sequence is required to excite a specific defect. Logical combinations (AND/OR) of specified pin excitations and fault propagation points may be employed. The excitation value list, the initial value list and the propagation point can include any of the following: input pins of an entity; output pins of the entity; nets inside of the entity; pins on usage blocks inside the entity; nets inside a usage of a lower entity; and pins inside a usage of a lower level entity. The method and system also provide a capability to define pattern faults for each entity in a hierarchial circuit definition,…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.