Digital phase lock loop having frequency offset cancellation circuitry
US5546433A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 1995 |
| Grant date | Aug 13, 1996 |
| Priority date | — |
| Expiry date | Mar 21, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/10
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A phase-lock loop (PLL) circuit can be locked on to a synthesizer frequency without decreasing the available range of the frequency differences which the PLL circuit can accommodate during a data receive mode. An analog-to-digital conveyer (ADC) receives an analog input signal and responds to a periodic clock signal by providing a corresponding digital output signal. A phase comparator is coupled to receive the ADC digital output signal and to provide a phase error signal which is representative of a phase error in the digital output signal. A filter accumulates the value of the phase error signal into a filter first register to generate a primary frequency error value. The filter further includes a filter second register for holding a secondary frequency error value (e.g., a value which corrects for an offset between a synthesizer frequency and the PLL free-running frequency). A primary digital-to-analog converter (DAC) converts a primary filter output value, which includes the primary frequency error value, to a corresponding primary analog output signal. A secondary DAC converts a secondary filter output value, which includes the secondary frequency error value from the filter s…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.