System and method for incrementing memory addresses in a computer system
US5546592A · kind A · utility
2Cited by
28References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 26, 1989 |
| Grant date | Aug 13, 1996 |
| Priority date | — |
| Expiry date | Jun 26, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for tracking a plurality of addresses. The system comprises a plurality of registers, each register storing a current address and having an input and an output. Each input is connected to a data bus through a first multiplexer and each output is connected to an address bus through a second multiplexer. The system further comprises an adder connected between the address bus and the first multiplexer. The adder increments a current address appearing on the address bus while the address in on the bus and generates a next address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.