method for fabricating an embedded vertical bipolar transistor and a memory cell
US5547893A · kind A · utility
46Cited by
6References
30Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 27, 1995 |
| Grant date | Aug 20, 1996 |
| Priority date | — |
| Expiry date | Dec 27, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/401
Abstract
The present invention provides a method of simultaneously forming CMOS DRAM cells, CMOS devices, and vertical bipolar transistors on the same chip. The invention utilities a CMOS DRAM process to simultaneously fabricate a vertical bipolar transistor and uses only one additional mask (a base implant mask) compared to forming the DRAM cell alone. Also, to reduce the bipolar collector plug resistance, the process uses a tungsten-plug module where the collector is formed within a field oxide region near the base.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.