CMOS processing with low and high-current FETs
US5547894A · kind A · utility
18Cited by
10References
6Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 21, 1995 |
| Grant date | Aug 20, 1996 |
| Priority date | — |
| Expiry date | Dec 21, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A method of processing CMOS circuits provides up to three types of transistors (standard NFETs, PFETs and high current NFETs) without additional masking steps by the simultaneous implantation of the standard PFET and the high current NFET low doped source and drain implants and a separate implantation of the standard NFET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.