William R. Tonti
293Patents
44h-index
189Co-inventors
93Inventor score
Filing activity: Apr 30, 1991 → Sep 20, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6544837B1 | SOI stacked DRAM logic | Emerging Cross-Sectional Technologies | 391 | Expired |
| US7790543B2 | Device structures for a metal-oxide-semiconductor field effect transistor and methods of fabricating such device structures | Electricity | 267 | Active |
| US6720213B1 | Low-K gate spacers by fluorine implantation | Emerging Cross-Sectional Technologies | 250 | Expired |
| US7790524B2 | Device and design structures for memory cells in a non-volatile random access memory and methods of fabricating such device structures | Electricity | 244 | Active |
| US6271059A | Chip interconnection structure using stub terminals | Electricity | 237 | Expired |
| US6429477B1 | Shared body and diffusion contact structure and method for fabricating same | Electricity | 169 | Expired |
| US6358627B2 | Rolling ball connector | Emerging Cross-Sectional Technologies | 149 | Expired |
| US6590258B2 | SIO stacked DRAM logic | Emerging Cross-Sectional Technologies | 141 | Expired |
| US6492211B1 | Method for novel SOI DRAM BICMOS NPN | Electricity | 135 | Expired |
| US7352034B2 | Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures | Electricity | 129 | Expired |
| US7818702B2 | Structure incorporating latch-up resistant semiconductor device structures on hybrid substrates | Electricity | 116 | Active |
| US5334880A | Low voltage programmable storage element | Physics | 98 | Expired |
| US6255899A | Method and apparatus for increasing interchip communications rates | Electricity | 98 | Expired |
| US6410431B1 | Through-chip conductors for low inductance chip-to-chip integration and off-chip connections | Electricity | 98 | Expired |
| US6141245A | Impedance control using fuses | Electricity | 86 | Expired |
| US6345362B1 | Managing Vt for reduced power using a status table | Emerging Cross-Sectional Technologies | 82 | Expired |
| US6114221A | Method and apparatus for interconnecting multiple circuit chips | Electricity | 81 | Expired |
| US7163851B2 | Concurrent Fin-FET and thick-body device fabrication | Electricity | 74 | Expired |
| US6399990B1 | Isolated well ESD device | Electricity | 71 | Expired |
| US7763531B2 | Method and structure to process thick and thin fins and variable fin to fin spacing | Physics | 66 | Active |
| US5894152A | SOI/bulk hybrid substrate and method of forming the same | Electricity | 65 | Expired |
| US6577156B2 | Method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox | Physics | 64 | Expired |
| US6876035B2 | High voltage N-LDMOS transistors having shallow trench isolation region | Electricity | 63 | Expired |
| US6555891B1 | SOI hybrid structure with selective epitaxial growth of silicon | Electricity | 62 | Expired |
| US6346846B1 | Methods and apparatus for blowing and sensing antifuses | Physics | 60 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.