Method for producing semiconductor device having DMOS and NMOS elements formed in the same substrate
US5550067A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 1993 |
| Grant date | Aug 27, 1996 |
| Priority date | — |
| Expiry date | Mar 29, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/111
Abstract
An intelligent power element has integrated DMOS transistors and control elements such as NMOS transistors. Impurity concentration inside a channel well (4) of each DMOS transistor is denser than that at the surface thereof. This results in reducing the reach-through withstand voltage of the DMOS transistor to less than that of the NMOS transistor. As a result, a reach-through phenomenon occurs on the DMOS transistor having a higher allowable (withstand) current before it occurs on the NMOS transistor having a lower allowable current. To provide the same effect, the reach-through withstand voltage of the DMOS transistor may be decreased by forming an internal high concentration well (201) at an upper part of a deep main well (31) of the DMOS transistor. The well (201) is shallower than the main well (31) and does not extend under a gate electrode (71).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.