Reduced mask DRAM process

US5550078A · kind A · utility

Assignee

• VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION · TW

Inventor

• Janmye Sung · Taipei, TW

Key dates

• Filing date: Jun 28, 1995
• Grant date: Aug 27, 1996
• Expiry date: Jun 28, 2015

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

A process for fabricating stacked capacitor DRAM devices has been developed in which self aligned storage node contact structures, as well as bit line contact structures, are featured. A split polysilicon process has also been used to allow maskless source and drain ion implantation processing to be realized, thus reducing the number of photolithographic steps. A dual dielectric, interlevel insulator, is used to eliminate leakage between metal levels.