Method for fabricating silicide shunt of dual-gate CMOS device
US5550079A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 15, 1995 |
| Grant date | Aug 27, 1996 |
| Priority date | — |
| Expiry date | Jun 15, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0177
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a silicide shunt for use in dual-gate CMOS devices makes use of a nitrogen-containing silicide layer overlying the juncture between the P-type polysilicon layer and the N-type polysilicon layer. The nitrogen-containing silicide layer is formed by implanting nitrogen-containing ions, such as .sup.28 N.sub.2.sup.+, into a partial or overall silicide shunt which was originally deposited over the P-type polysilicon layer and N-type polysilicon layer. Therefore, the nitrogen-containing silicide layer can serve as a diffusion barrier layer retarding the lateral dopant diffusion of these polysilicon layers via the silicide shunt.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.