Multiphase clock synthesizer having a plurality of phase shifted inputs to a plurality of phase comparators in a phase locked loop
US5550515A · kind A · utility
70Cited by
3References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 27, 1995 |
| Grant date | Aug 27, 1996 |
| Priority date | — |
| Expiry date | Jan 27, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-locked loop wherein the output signal is effectively sampled at an increased rate from conventional phase-locked loops, allowing for a greater increase in the ratio of the output frequency to the input frequency while reducing the possibility of jitter or failure to lock. Multiple differently phased reference signals and correspondingly phased feedback signals are produced. The comparison of the feedback signals and the reference signals produce multiple error signals which are combined to adjust the oscillation frequency of the voltage-controlled oscillator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.