Process for self-aligned source for high density memory
US5552331A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 1995 |
| Grant date | Sep 3, 1996 |
| Priority date | — |
| Expiry date | Jul 11, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/43
Abstract
An improved method for protecting the gate edge and adjacent source region of a semiconductor device is disclosed. In this method, spacers are formed along the gates of one type of transistor to protect the gate edge and adjacent source area during a self-aligned source etch. Spacers of a different width, which may be optimized for different voltage requirements, are formed along the gates of a second type of transistor of the same intergated circuit. This method is particularly applicable in the formation of EPROM, Flash EPROM, EEPROM, or other memory cells in conjunction with periphery devices needing to sustain relatively higher voltages. By decouplng the memory cell requirement from the periphery device requirement, tighter gate spacing and smaller cell size can be achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.