Built-in self-test for logic circuitry at memory array output
US5553082A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 1995 |
| Grant date | Sep 3, 1996 |
| Priority date | — |
| Expiry date | May 1, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/38
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Built-in self-testing of embedded logic circuitry at the output of an on-chip memory array is presented. Testing is accomplished by generating on chip a test pattern which is provided to the logic circuitry by writing at least a portion thereof into the memory array and then reading that portion out of the memory array, to the embedded logic circuitry. Three specific embodiments are presented, each of which employs a deterministic looping test pattern that comprises a portion of the generated test pattern. The looping test pattern may be either written through the memory array to the embedded logic circuitry or written around the memory array directly to the logic circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.