Method and apparatus for testing a clock stopping/starting function of a low power mode in a data processor
US5553236A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 1995 |
| Grant date | Sep 3, 1996 |
| Priority date | — |
| Expiry date | Mar 3, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A processor (10) has an internal clock circuit (12), a CPU (14), and a test controller (16). The CPU (14) has a low-power mode of operation and a normal mode of operation. When in low power mode, the internal clock circuit isolates the CPU clock (18) from the internal clock (28) and pulls the internal clock (28) to a stable logic state to ensure that the CPU is not changing state and consuming power. The test controller (16) can be in a low power mode along with the CPU (14) or in a normal mode while the CPU (14) is in the low power mode via the test control signal (26). When the CPU is in low power mode and the controller (16) is in normal mode, the controller (16) tests the operation of the circuit (12) to logically ensure that handling of the clock (18) is proper when entering, maintaining and exiting the low power mode of operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.