Juan Guillermo Revilla
35Patents
19h-index
37Co-inventors
77Inventor score
Filing activity: Nov 9, 1993 → Dec 21, 2007
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6173389A | Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor | Physics | 131 | Expired |
| US6216223A | Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor | Physics | 92 | Expired |
| US6460120B1 | Network processor, memory organization and methods | Electricity | 83 | Expired |
| US6151668A | Methods and apparatus for efficient synchronous MIMD operations with iVLIW PE-to-PE communication | Physics | 68 | Expired |
| US6606699B2 | Merged control/process element processor for executing VLIW simplex instructions with SISD control/SIMD process mode bit | Physics | 55 | Expired |
| US6081860A | Address pipelining for data transfers | Physics | 50 | Expired |
| US6101592A | Methods and apparatus for scalable instruction set architecture with dynamic compact instructions | Physics | 43 | Expired |
| US7313739B2 | Method and apparatus for testing embedded cores | Physics | 37 | Expired |
| US6557094B2 | Methods and apparatus for scalable instruction set architecture with dynamic compact instructions | Physics | 36 | Expired |
| US5884051A | System, methods and computer program products for flexibly controlling bus access based on fixed and dynamic priorities | Physics | 34 | Expired |
| US5925118A | Methods and architectures for overlapped read and write operations | Physics | 32 | Expired |
| US5862353A | Systems and methods for dynamically controlling a bus | Physics | 32 | Expired |
| US6467036B1 | Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor | Physics | 29 | Expired |
| US6851041B2 | Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor | Physics | 26 | Expired |
| US6219776A | Merged array controller and processing element | Physics | 25 | Expired |
| US6446191B1 | Methods and apparatus for efficient synchronous MIMD operations with iVLIW PE-to-PE communication | Physics | 24 | Expired |
| US5561614A | Method and apparatus for testing pin isolation for an integrated circuit in a low power mode of operation | Physics | 22 | Expired |
| US6775766B2 | Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor | Physics | 21 | Expired |
| US5623636A | Data processing system and method for providing memory access protection using transparent translation registers and default attribute bits | Physics | 19 | Expired |
| US6321322A | Methods and apparatus for scalable instruction set architecture with dynamic compact instructions | Physics | 19 | Expired |
| US7568141B2 | Method and apparatus for testing embedded cores | Physics | 17 | Active |
| US5553236A | Method and apparatus for testing a clock stopping/starting function of a low power mode in a data processor | Emerging Cross-Sectional Technologies | 17 | Expired |
| US7174429B2 | Method for extending the local memory address space of a processor | Physics | 16 | Expired |
| USRE41703E1 | Methods and apparatus for efficient synchronous MIMD operations with IVLIW PE-TO-PE communication | General | 16 | Expired |
| US5689659A | Method and apparatus for bursting operand transfers during dynamic bus sizing | Physics | 15 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.