Dual bus adaptable data path interface system
US5553249A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 1995 |
| Grant date | Sep 3, 1996 |
| Priority date | — |
| Expiry date | Mar 8, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0804
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single chip data path gate array interface links a central processing unit, operating at a first clock rate and single word protocol, to dual system busses operating at a second clock rate and multiple-word protocol. The data path interface holds command, data and message registers, controlled by external logic, in an input channel pathway and an output channel pathway. The interface chip is basically limited to registers and multiplexers making it flexible for use in different architectures such as both Store-Through and Non-Store-Through cache protocols. In addition, such a simplified chip is simple to fabricate and to maintain free of defects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.