Memory operations priority scheme for microprocessors
US5553268A · kind A · utility
15Cited by
6References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 14, 1991 |
| Grant date | Sep 3, 1996 |
| Priority date | — |
| Expiry date | Jun 14, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A structure and a method are provided to implement a memory bus arbiter, in which separate priorities are provided to instruction and data reads from the main memory. In one embodiment in a microprocessor with an on-chip cache, the present invention provides an arbiter which yields the memory bus, in decreasing priority order, to an ongoing bus transaction, a "direct memory access" (DMA) request, an instruction read resulting from a cache miss, a pending write request, and a read request, including reference to an uncacheable portion of memory and a data cache miss.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.