Power semiconductor device
US5554862A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 1994 |
| Grant date | Sep 10, 1996 |
| Priority date | — |
| Expiry date | Jan 19, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D18/40
Abstract
In a power semiconductor device, an n-base is formed on a p-emitter layer. On the n-base layer, a p-base layer, an n-emitter layer, and a high-concentration p-layer are formed laterally. In the p-base layer, an n-source layer is formed a specified distance apart from the n-emitter layer. In the n-emitter layer, a p-source layer is formed a specified distance apart from the high-concentration p-layer. A first gate electrode is formed via a first gate insulating film on the region sandwiched by the n-source layer and the n-emitter layer. A second gate electrode is formed via a second gate insulating film on the region sandwiched by the high-concentration p-layer and the p-source layer. On the p-emitter layer, a first main electrode is formed. A second main electrode is formed so as to be in contact with the p-base layer, the n-source layer, and the p-source layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.