Lead frame and semiconductor package with such lead frame
US5554886A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 7, 1995 |
| Grant date | Sep 10, 1996 |
| Priority date | — |
| Expiry date | Feb 7, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1815
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A lead frame and a semiconductor package produced using the lead frame are disclosed. The lead frame has a plurality of multi-layered inner leads, each of the multi-layered inner leads having at least two different metal layers joined to each other. An outer lead is formed by an extension part of at least one of the different metal layers of each of the multi-layered inner leads. The semiconductor package includes a semiconductor chip, the lead frame and a package body hermetically packaging a predetermined volume including the semiconductor chip, the multi-layered inner leads of the lead frame and a plurality of metal wires. The lead frame is free from chip paddle, thus to improve operational reliability of the package. The semiconductor package with the lead frame is readily enlarged in its memory capacity and mounted on the surface of a PCB in various mounting types.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.