Multiprocessor programmable interrupt controller system with separate interrupt bus and bus retry management
US5555420A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 1993 |
| Grant date | Sep 10, 1996 |
| Priority date | — |
| Expiry date | Dec 30, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor programmable interrupt controller system has an interrupt bus, distinct from the system (memory) bus, for handling interrupt request (IRQ) related messages. Each processor chip has an on-board interrupt acceptance unit (IAU) coupled to the interrupt bus to accept IRQs and to broadcast IRQs that it generates. I/O device interrupt lines are connected to one or more interrupt delivery units (IDUs) that are each coupled to the interrupt bus to broadcast I/O-generated IRQs. The interrupt bus is a synchronous three-wire bus having one clock wire and two wires for data transmission. Arbitration for control of the interrupt bus by the IAUs and IDUs uses one of the data wires. Lowest priority IRQ delivery mode uses a similar one-wire arbitration procedure for determining which IAU has the lowest current priority task running in its associated on-chip processor. A modification to this procedure also provides uniform distribution of IRQs to eligible processors. The actual servicing of the IRQs is done via the system bus. IAU acceptance logic is minimized by allowing retry of a delivered message when the acceptance latches are full. The increase in interrupt bus traffic due to…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.