Integrated circuits with a processor-based array built-in self test circuit
US5557619A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 4, 1994 |
| Grant date | Sep 17, 1996 |
| Priority date | — |
| Expiry date | Apr 4, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/44
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor-based Array Built-in Self Test (ABIST) circuit that generates self-test patterns for high speed SRAMs or DRAMs having a short access time. The circuit includes three main blocks: a conventional address generator for generating self-test addressing signals, a subset of which are used by a control logic main block. This control logic block forces proper signal sequencing of the processing main block during the ABIST mode. The processing main block includes, preferably, three generators for preparing signals for use during the next cycle. These signals are respectively stored in two latches to generate the corresponding expected output data one cycle later. The processor-based ABIST circuit allows for faster data generation, minimal semiconductor area consumption, extended programmability and full compatibility.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.