Patent · US Expired

Integrated circuit structure having at least one CMOS-NAND gate and method for the manufacture thereof

US5559353A · kind A · utility

11Cited by

6References

5Claims

0Family size

Assignee

Siemens Aktiengesellschaft · DE

Inventors

Lothar Risch · Neubiberg, DE
Thomas Vogelsang · Mountain View, US
Franz Hofmann · Munich, DE
Karl Robert Hofmann · Netphen, DE

Key dates

Filing date	Nov 1, 1994
Grant date	Sep 24, 1996
Priority date	—
Expiry date	Nov 1, 2014

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/856
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A first MOS transistor and a second MOS transistor are connected in series with a first complementary MOS transistor and a second complementary MOS transistor that are connected in parallel with one another. The transistors are each realized as a vertical layer sequence that forms the source, channel and drain and that which has a sidewall at which a gate dielectric and a gate electrode are arranged. The complementary MOS transistors connected in parallel with one another are realized in a common layer sequence of the source, channel and drain. The layer sequences that form the series-connected transistors are arranged above one another. The circuit structure is manufactured by epitaxal definition of the layer sequences, such as by molecular beam epitaxy.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.