Programmable logic array structure for semiconductor nonvolatile memories, particularly flash-eeproms
US5559449A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 21, 1995 |
| Grant date | Sep 24, 1996 |
| Priority date | — |
| Expiry date | Feb 21, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1772
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The PLA, which implements a state machine of a nonvolatile memory, presents a dynamic NAND-NOT-NOR configuration, and the timing signals for correct reading of the PLA are generated by a clock generator which generates a monostable succession of read enabling signals on receiving a predetermined switching edge of an external clock signal. The clock generator enables evaluation of the AND and OR planes of the PLA and subsequently storage of the results through sections duplicating the propagation delays of the signals in the corresponding parts of the PLA. Reading is terminated as soon as completion of the storage step is indicated, so that reading of the PLA lasts only as long as strictly necessary, thus preventing erroneous switching while at the same time ensuring correct reading of the PLA.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.