Low power clock circuit
US5559463A · kind A · utility
36Cited by
6References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 18, 1994 |
| Grant date | Sep 24, 1996 |
| Priority date | — |
| Expiry date | Apr 18, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0019
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
High-efficiency clock generator circuits having single or complementary outputs for driving capacitive loads. The clock generator has therein at least one pair of complementary FET switches, coupled between the output of the generator and power supply rails, and an inductor. The generator is operated at a frequency approximately equal the resonant frequency of the inductor combined with the capacitance of the load. Energy normally stored in the load and dissipated in the FETs as in conventional clock generators is instead stored in the inductor and returned to the loads for reuse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.