Dynamic random access memory with a simple test arrangement
US5559739A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 1995 |
| Grant date | Sep 24, 1996 |
| Priority date | — |
| Expiry date | Sep 28, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Dynamic Random Access Memory (DRAM) including an array of memory cells arranged in rows and columns, a word line in each row responsive to a row address and, a pair of complementary bit lines in each column. The DRAM also includes a sense amp in each column connected between a sense enable and the pair of complementary bit lines. The sense amp is a pair of cross coupled NFETs, with the sources of the NFETs connected to the sense amp enable. A bit line pre-charge is connected to each pair of complementary bit lines. The bit line pre-charge is connected between the complementary bit line pair and a reference voltage. A test control circuit selectively holds the sense amp disabled and the bit line pairs in a pre-charge state in response to a test control signal. An active sense amp load connected between the sense amp and a load enable latches data in the sense amp. The active sense amp load is a pair of cross coupled PFETs connected to the sense amp with the sources of the PFETs connected to the load enable. Optionally, each column may include a plurality of bit line pairs, each pair connected to a mux input. In this embodiment, the sense amp is connected between the mux's output a…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.