Timing control circuit for synchronous static random access memory
US5559752A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 1995 |
| Grant date | Sep 24, 1996 |
| Priority date | — |
| Expiry date | Aug 14, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A timing control circuit (10) is disclosed that provides a timing circuit (12) for controlling the operation of an I/O path circuit (14) in a synchronous static random access memory (SRAM). In a read or write operation, the timing circuit (12) sequentially disables bit line equalization circuits (34), enables sense amplifiers (38), disables I/O line equalization circuits (42), and enables secondary sense amplifiers (44). Further, the timing control (12) initiates a reset operation prior to the completion of the read or write operation. The reset operation includes sequentially enabling the bit line equalization circuits (34), disabling the sense amplifiers (38), enabling the I/O line equalization circuits (42), and disabling the secondary sense amplifiers (44). The timing circuit (12) includes first, second and third delay circuits (20, 22, and 24) to allow for minimum split times for bit line pairs (32) and I/O line pairs (40), and minimum secondary sense amplifier (44) sensing times.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.