Method and apparatus for a dynamic, multi-speed bus architecture in which an exchange of speed messages occurs independent of the data signal transfers
US5559967A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 1993 |
| Grant date | Sep 24, 1996 |
| Priority date | — |
| Expiry date | Mar 18, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L5/20
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In a computer bus arrangement in which a plurality of nodes are interconnected by communication links, control signals are exchanged between the nodes concerning the transmission rate of a data message to be transmitted and the reception rate capability of the nodes. The data message is passed to those nodes which have a reception rate capability which matches or exceeds the transmission rate associated with the message. The other nodes receive a mock data message at a rate within their capability. In order to aid in synchronization within the bus arrangement, the duration of the mock data message is the same as the data message received by the other nodes, even though they are transmitted at different rates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.