High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution
US5560032A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 1995 |
| Grant date | Sep 24, 1996 |
| Priority date | — |
| Expiry date | Mar 1, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution for enhanced resource utilization and performance throughput. The computer system architecture includes an instruction fetch unit for fetching program instruction sets. Each instruction set includes a plurality of fixed length instructions with a prescribed program order (in-order). The architecture also includes an instruction execution unit for dynamically examining the instruction sets and scheduling instructions for execution, including out-of-order execution, among a plurality of functional units. The data results of the executed instructions are concurrently distributed to a temporary buffer and a register file array and managed by associated control logic, including a register renaming unit, a dependency checker unit, done control unit, and retirement control unit. The architecture also optimizes the scheduling of data paths in accordance with the type of computational function, including integer, floating point, and boolean.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.