Ferroelectric integrated circuit
US5561307A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jul 18, 1994 |
| Grant date | Oct 1, 1996 |
| Priority date | — |
| Expiry date | Jul 18, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/682
Abstract
An oversize ferroelectric capacitor is located against the contact hole to the MOSFET source/drain in a DRAM. A barrier layer made of titanium nitride, titanium tungsten, tantalum, titanium, tungsten, molybdenum, chromium, indium tin oxide, tin dioxide, ruthenium oxide, silicon, silicide, or polycide lies between the ferroelectric layer and the source drain. The barrier layer may act as the bottom electrode of the ferroelectric capacitor, or a separate bottom electrode made of platinum may be used. In another embodiment in which the barrier layer forms the bottom electrode, an oxide layer less than 5 nm thick is located between the barrier layer and the ferroelectric layer and the barrier layer is made of silicon, silicide, or polycide. A thin silicide layer forms and ohmic contact between the barrier layer and the source/drain. The capacitor and the barrier layer are patterned in a single mask step. The ends of the capacitor are stepped or tapered. In another embodiment both the bottom and top electrode may be made of silicon, silicide, polycide or a conductive oxide, such as indium tin oxide, tin dioxide, or ruthenium oxide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.