Multilayer interconnection structure for a semiconductor device
US5561327A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 5, 1995 |
| Grant date | Oct 1, 1996 |
| Priority date | — |
| Expiry date | Sep 5, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multilayer interconnection structure for a semiconductor device improving the integration degree of the semiconductor device and reducing the contact resistance. This interconnection structure comprises a lower interconnection layer having a predetermined constant width, an insulating layer provided on the lower interconnection layer and having a contact hole which is vertically placed on the lower interconnection layer and has a width larger than that of the lower interconnection layer, and an upper interconnection layer laid on the insulating layer such that it is connected to the lower interconnection layer through the contact hole. The upper interconnection layer has an enlarged portion at each side of or at only a side of its section corresponding to the contact hole. The enlarged portion extends toward a longitudinal direction of the lower interconnection layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.