Integrated memory cube, structure and fabrication
US5563086A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 1995 |
| Grant date | Oct 8, 1996 |
| Priority date | — |
| Expiry date | Mar 17, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/10253
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated memory cube structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the functional appearance of a single, higher level memory chip. A memory/logic cube is formed having N memory chips and at least one logic chip, with each memory chip of the cube having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N.times.M memory devices appears at the cube's I/O pins. A corresponding fabrication technique includes an approach for facilitating metallization patterning on the side surface of the memory subunit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.