Method and apparatus for zero extension and bit shifting to preserve register parameters in a microprocessor utilizing register renaming
US5564056A · kind A · utility
34Cited by
6References
10Claims
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Key dates
| Filing date | Nov 2, 1994 |
| Grant date | Oct 8, 1996 |
| Priority date | — |
| Expiry date | Nov 2, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Register identification preservation in a microprocessor implementing register renaming. Multiplexing and control circuitry are implemented for manipulating data sources to be supplied to a microprocessor's functional units. The circuitry will generate zero extending for source data to an execution unit where a data source register specified is shorter than a general register size utilized by the microprocessor. Similarly, the multiplexing and control circuitry will shift bits of data from one location to another upon a source input to a functional unit in accordance with control signals designating such activity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.