Macrocell with product-term cascade and improved flip flop utilization
US5565792A · kind A · utility
14Cited by
11References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 6, 1994 |
| Grant date | Oct 15, 1996 |
| Priority date | — |
| Expiry date | Sep 6, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17704
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device having macrocells enables gate cascades between macrocells to occur with a faster signal transit time, while preserving the flip flop function of the cascaded macrocells by reallocating a redirectable flip flop reset product term to the flip flop input. All gate product terms are retained during cascading. The macrocell logic is optimized for fast signal transit with selectable flip flop clocking. Multiplex clocking and programming are done with fewer transistors in the signal path, further reducing signal transit time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.