Circuit with a single address register that augments a memory controller by enabling cache reads and page-mode writes
US5566318A · kind A · utility
14Cited by
17References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 2, 1994 |
| Grant date | Oct 15, 1996 |
| Priority date | — |
| Expiry date | Aug 2, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0893
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single address register control technique for a memory controller allows both cache "reads" and page-mode "writes" to be implemented without requiring separate hardware address registers for each function. Because both functions may be implemented with virtually no performance loss in a high performance memory system using a single address register, a comparator, and one additional register, the costs and other disadvantages inherent in otherwise replicating control registers are obviated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.