Process for forming a nonvolatile random access memory array
US5567636A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 27, 1995 |
| Grant date | Oct 22, 1996 |
| Priority date | — |
| Expiry date | Feb 27, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An NVRAM array (30) has a portion (31) associated with a drive line segment (DSL.sub.11). The drive line segment (DSL.sub.11) is coupled to a drive line (DL1) by a control transistor (32). The layout allows a conductive member (112) that is part of lo the drive line segment (DSL.sub.11) to be formed at about the same elevation as the memory capacitors (118). The layout further allows interconnects (136) for the drive lines (DL1, DL.sub.2) and bit lines (BL.sub.11, BL.sub.12, BL.sub.13, BL.sub.14) to be formed over the control and memory transistors (32, 34), as opposed to between the transistors. The process forms a small and reliable NVRAM device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.