Method of fabricating gate electrode of CMOS device
US5567642A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 1995 |
| Grant date | Oct 22, 1996 |
| Priority date | — |
| Expiry date | Nov 6, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/019
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a gate electrode of a CMOS device is disclosed including the steps of: sequentially forming a gate insulating layer, first conductive layer and protective layer on a semiconductor substrate; selectively etching a predetermined portion of the protective layer in which a PMOS transistor will be formed; forming a second conductive layer on the overall surface of said substrate; removing the second conductive layer formed on the protective layer, and partially etching the protective layer to a predetermined thickness; and patterning the second conductive layer, the protective layer, the first conductive layer and the gate insulating layer using a gate electrode pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.