Shadow register file for instruction rollback

US5568380A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Timothy B. Brodnax · Arlington, US
• John S. Bialas, Jr. · South Burlington, US
• Steven A. King · Sacramento, US
• Johnny LeBlanc · Austin, US
• Dale A. Rickard · Manassas, US
• Clark J. Spencer · Lučenec, SK
• Daniel L. Stanley · Manassas, US

Key dates

• Filing date: Aug 30, 1993
• Grant date: Oct 22, 1996
• Expiry date: Aug 30, 2013

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F11/1407
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A fault-tolerant computer system having shadow registers for storing the contents of a primary array into a shadow array at the completion of a stored instruction execution. This is accomplished in one clock cycle with all registers being shadowed simultaneously. During rollback of execution steps for a checkpoint retry, the shadow register files provide a signal cycle unload of the shadow array into the primary array. LSSD latches are used in the shadow register file.